A test for a semiconductor integrated circuit (described LSI hereinafter) is largely classified to a function test for checking a logical function for the circuit and a DC test for checking of leakage from an input pin or of output voltage level. Those tests are generally performed by using a commercially available tester (described an LSI tester hereinafter).
FIG. 11 is a simulated view showing a connectional relation between a conventional type of LSI and LSI tester. The LSI tester 1 comprises pin electronics 11 enabling generation and monitoring of signal waveforms for performing a function test, a DC measuring unit 12 provided separately from the pin electronics 11 for DC measurement, and relays 14 provided at midpoint of signal lines 13 respectively.
When a function test is performed, the relays 14 are switched to the pin electronics 11, by which the signal pins 21 of the LSI 2 are connected to the pin electronics 11 of the LSI tester 1 through the relays 14 so that the signal pins 21 are in one-to-one correspondence with the pin electronics 11.
On the other hand, when a DC test is performed, the relays 14 are successively switched to the DC measuring unit 2 one after another. With this operation, the signal pins 21 of the LSI 2 are successively connected to the DC measuring unit 12 through each relay 14 switched to the DC measuring unit 12. FIG. 11 shows a state where the topmost signal pin 21 of the LSI 2 is connected to the DC measuring unit 12.
Description is made herein for the DC test. The DC test has three types of tests: a pin contest for checking connection between the LSI tester and LSI, an input leak test for checking whether there is failure as current leakage to an input pin of the LSI, and an output voltage test for checking a voltage level output from an output pin of the LSI.
FIG. 12 is a view showing an outline of the pin contest, and the reference numerals Dl and D2 show protective diodes provided in the power unit VDD and a ground GND of the signal pin section in the LSI 2 respectively. In the pin contest a voltage V1 being generated in the protective diode Dl when a current I1 is supplied to the LSI 2 through the signal pin 21 from the DC measuring unit 12 of the LSI tester 1 and a voltage V2 being generated in the protective diode D2 when a current I2 is taken out from the LSI 2 is measured, and connection between the LSI tester 1 and LSI 2 are checked according to those measured values.
FIG. 13 is a view showing an outline of the input leak test. The input leak test provides a potential at a relatively lower level (corresponding to "0") or at a relatively higher level (corresponding to "1") to the signal pin 21 of the LSI 2 using the DC measuring unit 12, and checks the current flowing at that point of time. When there is resistive short-circuiting failure to the power unit VDD (shown as resistance R1 in FIG. 13), a current I3 flows into the LSI tester 1 when "0" is provided to the signal pin 21, and when there is resistive short-circuiting failure to the ground GND (shown as resistance R2 in FIG. 13), a current I4 flows into the LSI 2 when "1" is provided to the signal pin.
FIG. 14 is a view showing an outline of the output voltage test, and in this test, a current I5 is drawn out to the LSI tester 1 when the voltage output from the signal pin is "1", on the other hand, when voltage output from the signal pin is "0", a voltage level is checked while a current I6 is provided to the LSI 2. Assuming that resistance of the gate G1 is Rp when it becomes ON when the output voltage is "1", the voltage when this gate G1 is ON can be expressed with the following expression (1), and assuming that resistance of the gate G2 is Rn when it becomes ON when the output voltage is "0", the voltage when this gate G2 is ON can be expressed with the following expression (2). EQU Voltage=VDD-Rp.times..vertline.I5.vertline. (1) EQU Voltage=Rn.times..vertline.I6.vertline. (2)
The output voltage test checks whether the values of Rp and Rn according to the expressions (1) and (2) are within a normal range or not.
The scale of integration in LSI is dramatically becoming larger in recent years, and in association with that number of signal pins is becoming larger, and therefore there has arisen a case where the number of signal pins of the LSI exceeds the number of pin electronics prepared for the existing LSI tester. In that case, in the conventional type of LSI tester, there may occur a problem that some signal pins in the LSI can not be connected to the LSI tester, so that it is difficult to test the LSI, but it is possible to perform the function test by incorporating self-test capabilities inside the LSI in place of the conventional method using the LSI tester. In this case, only some signal pins are sufficient for inputting a clock signal and a control signal into the LSI from the outside.
As for the DC test, however, there is no solution so far for a case where a number of signal pins of LSI is larger than a number of pin electronics of an LSI tester, and therefore the DC test can not be performed.